Thin film transistor, manufacturing method of same, and display device

ABSTRACT

According to one embodiment, a thin film transistor includes: a substrate; a semiconductor layer; first and second insulating films; and gate, source and drain electrodes. The semiconductor layer is provided on the substrate. The semiconductor layer is made of an oxide having indium. The semiconductor layer has first and second regions and other region. The first insulating film covers a top face of the other region. The second insulating film covers at least a pair of side surfaces of the semiconductor layer. The second insulating film is formed under a condition different from that for the first insulating film. The gate electrode is provided on the first and second insulating films or below the semiconductor layer. The source and drain electrodes are provided on the first and second regions, respectively. The drain and source electrodes sandwich the pair of the side surfaces of the semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2011-045567, filed on Mar. 2,2011; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a thin film transistor,a manufacturing method of the same, and a display device.

BACKGROUND

Thin film transistors (TFTs) are widely used in a liquid crystal displaydevice, an organic electroluminescent display device, or the like.Particularly, TFTs using amorphous silicon for an active layer are nowwidely used in large-sized liquid crystal display devices. It is desiredto implement a novel active layer that can meet further upsizing, higherreliability, higher mobility, and so on in future.

In—Ga—Zn—O amorphous oxides, for example, can be formed on a plasticsubstrate because the oxides can be formed in a film at low temperature,and the oxides are transparent in a visible wave range. Thus, it islikely to implement a transparent TFT using the oxides for asemiconductor layer. This TFT obtains the mobility ten times themobility of amorphous silicon or more. Problems of practical applicationare to further improve uniformity and reliability.

For a method for improving reliability, there is proposed a techniquethat prevents a phenomenon in which heat treatment causes the oxygenconcentration of a semiconductor layer to change, resulting indeterioration of the characteristics. This technique stabilizes thecharacteristics by covering a semiconductor layer with a good qualityinsulating layer (a channel protective film).

However, in this configuration, in the process of processing asemiconductor layer before forming a channel protective film, at leastthe upper layer of the semiconductor layer is subjected to cleaning withwater, and the semiconductor layer absolves moisture. The oxidesemiconductor tends to take moisture in the film because of thecharacteristics, so that it is necessary to control moisture in thefilm.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view illustrating a thin film transistor accordingto a first embodiment;

FIG. 2 is a diagram illustrating a cross section on line II-II shown inFIG. 1;

FIG. 3 is a schematic plane view illustrating a thin film transistor acomparative example;

FIG. 4 is a diagram illustrating a cross section on line IV-IV shown inFIG. 3;

FIG. 5 is a diagram illustrating a characteristic when a leak current isgenerated in a thin film transistor;

FIG. 6A is a diagram illustrating a film forming condition for the firstchannel protective film; FIG. 6B is a diagram illustratingcharacteristics of the thin film transistors made by each film formingcondition;

FIG. 7A to 7D are diagrams illustrating a manufacturing method for thethin film transistor according to the first embodiment;

FIG. 8 is a schematic plane view illustrating a thin film transistoraccording to a second embodiment;

FIG. 9 is a diagram illustrating a cross section on line IX-IX shown inFIG. 8;

FIG. 10A to 10D are diagrams illustrating a manufacturing method for thethin film transistor according to the second embodiment;

FIG. 11 is a schematic plane view illustrating a thin film transistoraccording to a third embodiment;

FIG. 12 is a diagram illustrating a cross section on line XII-XII shownin FIG. 11;

FIG. 13 is a schematic plane view illustrating a thin film transistoraccording to a fourth embodiment;

FIG. 14 is a diagram illustrating a cross section on line XIV-XIV shownin FIG. 13;

FIG. 15A is a diagram illustrating a picture circuit using a thin filmtransistor; FIG. 15B is a diagram illustrating a cross section of adisplay device;

FIG. 16 is a diagram illustrating a cross section of a part of a TFTobserved with of an SEM;

FIG. 17 is a diagram illustrating a cross section of a part of a TFTobserved with an SEM after the TFT is processed using dilute hydrogenfluoride;

FIG. 18A to FIG. 18D are schematic views illustrating an InGaZnO filmbefore and after annealed;

FIG. 19 is a schematic plane view illustrating a thin film transistoraccording to a sixth embodiment; and

FIG. 20A to 20D are diagrams illustrating a manufacturing method for thethin film transistor according to the sixth embodiment.

DETAILED DESCRIPTION

In general, according to one embodiment, a thin film transistorincludes: a substrate, a semiconductor layer, a first insulating film, asecond insulating film, a gate electrode, a source electrode, and adrain electrode. The semiconductor layer is provided on the substrate.The semiconductor layer is made of an oxide having indium for a maincomponent. The semiconductor layer has a top face facing the substrateand a pair of side face.

The top face has a first region, a second region, and an other regionexcept the first region and the second region. The first insulating filmcovers the other region of the semiconductor layer. The secondinsulating film covers at least the pair of side surfaces of thesemiconductor layer. The second insulating film is formed under acondition different from a condition for the first insulating film. Thegate electrode is provided on the first insulating film and the secondinsulating film or provided below the semiconductor layer. The sourceelectrode is provided on the first region. The drain electrode isprovided on the second region. The drain electrode faces the sourceelectrode. The drain electrode and the source electrode sandwiches thepair of the side surfaces of the semiconductor layer.

According to another embodiment, a manufacturing method for a thin filmtransistor is disclosed. The method can process. The processingincludes: forming a semiconductor layer made of an oxide having indiumfor a main component on a gate electrode on a substrate via a gateinsulating layer, forming a first insulating film on a top face except asource electrode contact region and a drain electrode contact region ofthe semiconductor layer, and forming a second insulating film coveringat least a pair of side surfaces of the semiconductor layer under acondition different from a condition for the first insulating film; orforming a semiconductor layer made of an oxide having indium for a maincomponent on a substrate, forming a first insulating film on a top faceexcept a source electrode contact region and a drain electrode contactregion of the semiconductor layer, forming a second insulating filmcovering at least a pair of side surfaces of the semiconductor layerunder a condition different from a condition for the first insulatingfilm, and forming a gate electrode on the second insulating film. Themethod can form a source electrode on the source electrode contactregion of the semiconductor layer. In addition, the method can form adrain electrode on the drain electrode contact region of thesemiconductor layer so as to face the source electrode to sandwich apart of the side surfaces of the semiconductor layer.

According to another embodiment, a display device includes a thin filmtransistor and a display layer. The thin film transistor includes asubstrate, a semiconductor layer, a first insulating film, a secondinsulating film, a gate electrode, a source electrode, and a drainelectrode. The semiconductor layer is provided on the substrate. Thesemiconductor layer is made of an oxide having indium for a maincomponent. The semiconductor layer has a top face facing the substrateand a pair of side face. The top face has a first region, a secondregion, and an other region except the first region and the secondregion. The first insulating film covers the other region of thesemiconductor layer.

The second insulating film covers at least the pair of side surfaces ofthe semiconductor layer. The second insulating film is formed under acondition different from a condition for the first insulating film. Thegate electrode is provided on the first insulating film and the secondinsulating film or below the semiconductor layer. The source electrodeis provided on the first region. The drain electrode is provided on thesecond region. The drain electrode faces the source electrode. The drainelectrode and the source electrode sandwiches the pair of the sidesurfaces of the semiconductor layer. The display layer is configured tocause at least one of optical emission and a change in an opticalproperty including at least one of birefringence, optical activity,scattering property, diffraction property, and optical absorption,according to at least one of a voltage and a current supplied throughthe thin film transistor.

Exemplary embodiments of the invention will now be described in detailwith reference to the drawings.

The drawings are schematic or conceptual; and the relationships betweenthe thickness and width of portions, the proportions of sizes amongportions, etc., are not necessarily the same as the actual valuesthereof. Further, the dimensions and proportions may be illustrateddifferently among the drawings, even for identical portions.

In the specification and the drawings of the application, componentssimilar to those described in regard to a drawing thereinabove aremarked with like reference numerals, and a detailed description isomitted as appropriate.

First Embodiment

FIG. 1 is a schematic view illustrating the configuration of a bottomgate TFT according to a first embodiment.

FIG. 2 is a diagram illustrating a cross section on line II-II shown inFIG. 1.

As illustrated in FIG. 1 and FIG. 2, a TFT 11 according to the firstembodiment includes an insulating layer 110, a gate electrode 120provided on the insulating layer 110, a gate insulating layer 130covering the gate electrode 120, and a semiconductor layer 140 providedon the gate insulating layer 130. The TFT 11 includes a channelprotective film 150 covering the semiconductor layer 140, and a sourceelectrode 161 and a drain electrode 162 electrically connected to thesemiconductor layer 140, the source electrode 161 and the drainelectrode 162 being provided apart from each other so as to sandwich thegate electrode 120 therebetween.

The channel protective film 150 includes a first channel protective film151 (a first insulating film), and a second channel protective film 152(a second insulating film). The first channel protective film 151 coversthe top face of the semiconductor layer 140 except a source electrodecontact region 140S (a first region) and a drain electrode contactregion 140D (a second region). The second channel protective film 152covers at least a pair of edges 140E (the side surfaces) of thesemiconductor layer 140. The pair of the edges 140E are positionedbetween the source electrode 161 and the drain electrode 162 of thesemiconductor layer 140. In this example, the second channel protectivefilm 152 further covers the first channel protective film 151 as well.The second channel protective film 152 has an oxidation state higherthan the oxidation state of the first channel protective film 151.

For example, the oxygen concentration of the second insulating film (thesecond channel protective film 152) is higher than the oxygenconcentration of the first insulating film (the first channel protectivefilm 151).

As illustrated in FIG. 1 and FIG. 2, the thin film transistor 11according to this embodiment includes a substrate 100, the semiconductorlayer 140, the first insulating film (the first channel protective film151, for example), the second insulating film (for example, the secondchannel protective film 152), the gate electrode 120, the firstelectrode (the source electrode 161, for example), and the secondelectrode (the drain electrode 162, for example).

The semiconductor layer 140 is provided on the substrate 100. Thesemiconductor layer 140 contains an oxide including indium. Thesemiconductor layer 140 has a first portion 41, a second portion 42, anda middle portion 43. The first portion 41 and the second portion 42 areprovided on a plane in parallel with the major surface of the substrate100. The middle portion 43 is provided between the first portion 41 andthe second portion 42. The semiconductor layer 140 has a top face 140U,a first side face 140E1 of the middle portion 43, and a second side face140E2 of the middle portion 43. The top face 140U includes the firstregion (the source electrode contact region 140S) on the first portion41, the second region (the drain electrode contact region 140D) on thesecond portion 42, and an other region 1401 except the first region andthe second region. The second side face 140E2 and the first side face140E1 are arranged side by side along a second direction vertical to afirst direction from the first portion 41 toward the second portion 42,the first direction being in parallel with the aforementioned plane.

The first insulating film covers the other region 1401. The secondinsulating film covers at least the first side face 140E1 and the secondside face 140E2. The second insulating film is formed under theconditions different from the conditions for the first insulating film.The gate electrode 120 faces the semiconductor layer 140. The firstelectrode is provided on the first region. The second electrode isprovided on the second region.

Although the insulating layer 110 and the gate electrode 120 are notshown in FIG. 1, the insulating layer 110 and the gate electrode 120 areprovided on the back of the gate insulating layer 130 on the paper. InFIG. 1, the position of the first channel protective film 151 and theposition of the semiconductor layer 140 are indicated by broken lines.

The semiconductor layer 140 contains an oxide including indium and atleast one of gallium (Ga), zinc (Zn), tin (Sn), and silicon (Si).Namely, the semiconductor layer 140 is an oxide film containing In, Ga,and Zn, for example, (i.e. an In—Ga—Zn—O oxide film). The semiconductorlayer 140 may be an oxide film containing In and Zn (i.e. an In—Zn—Ooxide film). The semiconductor layer 140 may be an oxide film containingIn, Zn, and Si (i.e. an In—Zn—Si—O oxide film). In the following,In—Ga—Zn—O oxide films are generically called “an InGaZnO film”. TheInGaZnO film used below has In as a main component.

The insulating layer 110 can be formed on the substrate. A lighttransmitting glass substrate, a light transmitting plastic substrate, acomposite substrate that a thin piece of glass (a thickness of 10 μm) isbonded to a plastic substrate, or the like, for example, can be used forthe substrate. In addition to these, a light shielding substrate such asa substrate made of silicon or stainless steel may be used.Alternatively, an insulating substrate may be used as well for theinsulating layer 110. In this embodiment, it is sufficient that thesurface of the portion on which the gate electrode 120 is provided hasinsulating properties.

A high melting point metal such as MoW, Ta, and W, for example, can beused for the gate electrode 120. Hillock-free Al alloy or Cu of a lowerresistance may be used. However, a given conductive material can be usedfor the gate electrode 120, not limited thereto.

For the gate insulating layer 130, an insulating material such assilicon oxide (SiO_(x)), silicon nitride (SiN_(x)), and siliconoxynitride, for example, can be used.

For the first channel protective film 151, an insulating materialcontaining oxygen such as silicon oxide, for example, with acidresistance higher than the acid resistance of the semiconductor layer140 can be used. Preferably, the interface between the semiconductorlayer 140 and the first channel protective film 151 has good quality inorder to obtain excellent characteristics in the TFT 11.

Silicon oxide or the like with acid resistance higher than the acidresistance of the semiconductor layer 140 is also used for the secondchannel protective film 152. An exemplary method for forming the secondchannel protective film 152 in a film with an oxidation state higherthan the oxidation state of the first channel protective film 151 willbe described later.

A given conductive material can be used for the source electrode 161 andthe drain electrode 162. For example, a given conductive stacked filmsuch as a Ti/Al/Ti film, Mo/Al/Mo film, or the like can be used.

It may be possible to provide a resin passivation film such as siliconoxide or polyimide, for example, so as to cover the TFT 11, in order toimprove the durability of the TFT 11.

The TFT 11 particularly using In—Ga—Zn—O amorphous oxides among oxidesfor the semiconductor layer 140 is sensitive to moisture in the film.

The detailed study of the characteristics of the TFT revealed that thecharacteristics of the TFT greatly fluctuate according to the conditionsof forming a SiO₂ film on an InGaZnO film by plasma enhanced chemicalvapor deposition (PE-CVD) using SiH₄ gas and N₂O gas. Thus, desirably,the first channel protective film 151 is formed under the film formingconditions optimized for developing excellent TFT characteristics.

However, it is revealed that in the case where a damaged portion and amoisture absorbed portion in the channel edges 140E or the like of theInGaZnO film are covered with a film formed under the optimized filmforming conditions, a problem arises in that the resistance of the edges140E is decreased and the threshold voltage of the TFT characteristicsare negatively shifted. Although this problem can be improved byapplying heat treatment at a temperature of 200° C. or more, forexample, it is difficult to apply a sufficient heat treatment in thecase of using a substrate of a poor heating resistance such as a plasticsubstrate.

However, it was revealed that the resistance of the edges 140E is notdecreased by providing a film covering portions such as the edges 140Ewhere the resistance tends to be decreased in such a way that the filmforming conditions are changed as by decreasing the SiH₄/N₂O gas ratio,for example.

It is estimated that the width (the distance) from the film ends of theedges 140E is 1 μm or less, even though the resistance of the edges 140Eis increased, so that an effective decrease in the channel width can begenerally ignored.

In this embodiment, it is possible that the first channel protectivefilm 151 is formed on the semiconductor layer 140 under the conditionsof optimizing the TFT characteristics and the semiconductor layer 140 iscovered with the second channel protective film 152 formed under theconditions of increasing the resistance of the edges 140E of thesemiconductor layer 140. Consequently, according to this embodiment, itis possible to obtain the TFT 11 of high reliability. The first channelprotective film 151 and the second channel protective film 152 preventwater from penetrating the lower layer.

FIG. 3 shows a plane view of a TFT 211 having another configuration forcomparison.

FIG. 4 shows a cross sectional view on line IV-IV shown in FIG. 3.

This TFT 211 includes an insulating layer 210, a gate electrode 220provided on the insulating layer 210, a gate insulating layer 130provided on the gate electrode 220, a semiconductor layer 240 providedon the gate insulating layer 130, a channel protective film 250 coveringthe top face and edges 240E of the semiconductor layer 240, and a sourceelectrode 261 and a drain electrode 262 electrically connected to thesemiconductor layer 240, the source electrode 261 and the drainelectrode 262 being provided apart from each other so as to sandwich thegate electrode 220 therebetween.

Although the insulating layer 210 and the gate electrode 220 are notshown in FIG. 3, the insulating layer 210 and the gate electrode 220 areprovided on the back of the gate insulating layer 230 on the paper.Although the semiconductor layer 240 is not shown as well in thedrawing, the semiconductor layer 240 is provided on the back of the gateinsulating layer 230 on the paper.

It was revealed this time in this TFT 211 that the resistance of theedges 240E of the InGaZnO film forming the semiconductor layer 240 issometimes decreased to cause a leakage current indicated by arrows inFIG. 3.

The characteristics of the TFT 211 are shown in FIG. 5.

The horizontal axis shown in FIG. 5 expresses a gate voltage VG, and thevertical axis expresses a drain current I. Solid lines express thecharacteristics in the case where a leakage current is produced, and abroken line expresses the characteristics in the case where no leakagecurrent is produced.

The characteristics in two cases express the gate voltage VG up to avoltage of 10 V (volt). When a leakage current is produced, such adefective occurs that the threshold of the edges 240E of thesemiconductor layer 240 is negatively shifted.

As described above, in the TFT 11 using an InGaZnO film for thesemiconductor layer 140, the characteristics greatly fluctuate accordingto the conditions of forming SiO₂ (the first channel protective film151) on the InGaZnO film.

FIG. 6A shows the PE-CVD conditions of forming a SiO₂ first channelprotective films 151 on an InGaZnO film. FIG. 6B shows the TFTcharacteristics using the first channel protective films 151 formedunder the conditions.

As shown in FIG. 6A, three film forming conditions (conditions C-1 toC-3) were used. Marks indicated in curves in FIG. 6B correspond to marks(the conditions C-1 to C-3) indicated in FIG. 6A.

For a process of forming the TFT, a method in a first embodimentdescribed in JP-A (Kokai) 2010-123748 was used. The first channelprotective film 151 was formed by PE-CVD using a SiH₄ gas and a N₂O gas.Here, the optimum conditions are the condition C-2 in FIG. 6A. Thethresholds of the TFT characteristics are positively shifted if the SiH₄ratio is decreased more than the SiH₄ ratio of the condition C-2. It wasrevealed that the threshold voltage of the TFT characteristics arepositively shifted as the substrate temperature is more decreased andpower (RF power at power-on) is more increased under the same gasconditions.

Namely, the flow ratio of the source gas containing Si in the entiresource gas is decreased, the film forming rate is decreased, or the filmforming temperature is lowered, so that the thresholds of the TFTcharacteristics can be positively shifted. It is considered that thethresholds of the TFT characteristics are positively shifted as theoxidation state of Si in the film is higher, that is, the element ratioof O/Si is higher.

As described above, in the case of the TFT using the first channelprotective film 151, it is possible to improve the TFT characteristicsby optimizing the conditions of forming the first channel protectivefilm 151.

In the following, an exemplary manufacturing method for the TFTaccording to this embodiment will be described.

FIG. 7A, FIG. 7B, FIG. 7C, and FIG. 7D are schematic cross sectionalviews illustrating the process steps of a manufacturing method for theTFT according to the first embodiment.

These cross sections correspond to the cross section on line VII-VIIshown in FIG. 1.

First, for example, SiO₂ is formed in a film for the insulating layer110 on the major surface of the substrate 100 made of PEN (polyethylenenaphtahalate) by sputtering, for example. After that, an Al film and aMo film to be the gate electrode 120 are formed in a thickness of 150 nmand a thickness of 30 nm, respectively, by sputtering for stacking.

Subsequently, as illustrated in FIG. 7A, the gate electrode 120 isprocessed in a predetermined pattern. Photolithography is used for thisprocessing, and a mixed acid of phosphoric acid, acetic acid, and nitricacid is used for etching.

After that, a SiO₂ film to be the gate insulating layer 130 is formed ina thickness of 300 nm, for example, by PE-CVD using TEOS (Tetra EthylOrtho Silicate), for example. The film forming temperature in this filmformation is set at a temperature of 160° C. in consideration of theheat-resisting properties of PEN. A SiO₂ film having a thickness of 50nm was formed on the SiO₂ film by sputtering.

It is noted that the topmost layer of the gate insulating layer 130affects the film characteristics of the semiconductor layer 140 formedon the top face of the topmost layer. In this embodiment, desirably, thetopmost layer of the gate insulating layer 130 is a smooth film as muchas possible with a small hydrogen content.

On the SiO₂ film, an InGaZnO film (an In₂O₃—Ga₂O₃—ZnO film, for example)to be the semiconductor layer 140 is formed in a thickness of 30 nm, forexample, by reactive DC sputtering. In this film formation, thecomposition ratio of targets used is 1:1:1 at the atom number ratio ofIn:Ga:Zn. This film was formed in an atmosphere containing oxygen andargon, and the ratio of oxygen was about 1%, for example, to argon. Thefilm forming temperature is a temperature of about a few tens° C.,because heat treatment or the like is not particularly applied.

A SiO₂ film to be the first channel protective film 151 is formed in athickness of 30 nm, for example, by PE-CVD using a SiH₄ gas and a N₂Ogas (source gases). Desirably, the semiconductor layer 140 and the firstchannel protective film 151 are formed in Vacuum In-Situ Processingwithout exposing the interface to atmosphere as much as possible. Thefirst channel protective film 151 is used for a barrier film againstwater in processing the semiconductor layer 140 described later.

Desirably, the film thickness of the first channel protective film 151is 10 nm or more in order to maintain sufficient barrier properties. Inthe case of using a film having a thickness of 10 nm or less, it islikely that water is penetrated in processing the semiconductor layer140 due to a defect of the particle origin or the like and variationsoccur in the characteristics. If the thickness of the first channelprotective film 151 is thick, etching damage might be produced in thesemiconductor layer 140 and the gate insulating layer 130 below thesemiconductor layer 140 in etching the first channel protective film151.

For example, in the case of RIE using chlorine gas (Reactive IonEtching) described later, if the first channel protective film 151 isthick, etching is performed too much to the gate insulating layer 130 inthe lower layer, in consideration of the film thickness distribution ofthe first channel protective film 151 and the etching rate distributionof RIE. As decried later, also in etching the second channel protectivefilm 152, the gate insulating layer 130 is etched by the film thicknessof the first channel protective film 151. In this embodiment,preferably, the thickness of the first channel protective film 151 is 50nm or less.

Subsequently, as shown in FIG. 7B, the first channel protective film 151and the semiconductor layer 140 are continuously processed in apredetermined shape. RIE mainly using a chlorine gas, for example, isused for this etching. In consideration of the coverage of the secondchannel protective film 152 in the process steps described later, noside etch is to be produced in the semiconductor layer 140 (the InGaZnOfilm layer).

After this processing, a SiO₂ film to be the second channel protectivefilm 152 is formed throughout the surface by PE-CVD using a SiH₄ gas anda N₂O gas (source gases). For the film forming conditions in this filmformation, such conditions are used that the gas ratio of SiH₄/N₂O isdecreased with respect to the aforementioned film forming conditions forthe first channel protective film 151. The second channel protectivefilm 152 is formed under these conditions, so that the resistance of theInGaZnO film is increased. It is important to use these conditions.

For example, the first channel protective film 151 is formed using aSiH₄ gas and a N₂O gas in which the ratio of a SiH₄ gas flow rate to aN₂O gas flow rate (SiH₄ flow rate/N₂O flow rate) is used for a firstvalue. The second channel protective film 152 is formed using a SiH₄ gasand a N₂O gas in which the ratio of a SiH₄ gas flow rate to a N₂O gasflow rate (SiH₄ flow rate/N₂O flow rate) is used for a second valuelower than a first value.

For example, the first channel protective film 151 is formed using a gascontaining silicon and oxygen in which the ratio of a silicon quantityto an oxygen quantity (silicon quantity/oxygen quantity) is used for afirst value. The second channel protective film 152 is formed using agas containing silicon and oxygen in which the ratio of a siliconquantity to an oxygen quantity is used for a second value lower than thefirst value.

After that, as shown in FIG. 7C, the second channel protective film 152and the first channel protective film 151 are processed in apredetermined shape. Thus, the semiconductor layer 140 having a portioncontacted with the source electrode 161 and a portion contacted with thedrain electrode 162 is exposed. For this processing, RIE was used inwhich a CF₄ gas is a main component. It is known that the InGaZnO filmis hardly etched in typical RIE using a CF₄ gas.

After this processing, a Mo film (30 nm), an Al film (200 nm), and a Mofilm (50 nm) to be the source electrode 161 and the drain electrode 162are formed by sputtering.

As illustrated in FIG. 7D, these films are formed in a predeterminedshape, and then the TFT 11 is completed.

Since the TFT 11 immediately after processed is damaged by ultravioletrays or the like in processing, annealing (heat treatment) is performedin an annealing chamber at a temperature of about 150° C. for one hour.

For example, in this embodiment, annealing is performed in a nitrogenatmosphere in which oxygen is removed. Thus, it is possible to suppressdeterioration such as coloring in the exposed portions around theplastic substrate or the like. The characteristics of the TFT 11 have noproblem even though annealing is performed in a dry atmosphere. Afterthis processing, although not shown in the drawing, a passivation filmis appropriately formed on the top face.

In the oxide TFT, excellent characteristics can be obtained withoutperforming heating such as annealing particularly. However, inconsideration of long-term reliability, desirably, annealing isperformed at a temperature of 150° C. or more, for example, as describedabove. In detailed study, it was confirmed that hydrogen moves(diffuses) in the InGaZnO film and the SiO₂ film therearound (i.e. thegate insulating layer 130, the first channel protective film 151, thesecond channel protective film 152, or the like). It was revealed thatthe move of hydrogen affects the characteristics of the InGaZnO-TFT.

However, it was revealed that the InGaZnO film is processed in apredetermined shape and then a first annealing is performed, resultingin that the hydrogen concentration is distributed due to the processedshape or size of the InGaZnO film and the characteristics depends on thesize of the TFT, for example, because the diffusivity of hydrogen aredifferent in the InGaZnO film and SiO₂.

A PECVD-SiO₂ film, which is a film formed at low temperature, at atemperature of about 200° C. or less, using SiH₄ or TEOS for a sourcegas, contains about 0.1 at % of hydrogen in the film. On the other hand,the hydrogen content of the InGaZnO film formed by sputtering is muchsmaller than the hydrogen content of the PECVD-SiO₂ film. It is shownthat when the InGaZnO film is processed and annealed, and then hydrogenis diffused in this state, the hydrogen concentration is differentbetween the end and the center in the pattern of the InGaZnO film.

FIG. 18A to FIG. 18D are top views and cross sectional views showing anInGaZnO film before and after annealed.

FIG. 18A is a top view showing a gate insulating layer 130 and anInGaZnO film (a semiconductor layer 140) before annealed. FIG. 18C is across sectional view on line A-A′ in FIG. 18A. FIG. 18B is a top viewshowing the gate insulating layer 130 and the InGaZnO film (thesemiconductor layer 140) after annealed. FIG. 18D is a cross sectionalview on line B-B′ in FIG. 18B.

As illustrated in FIG. 18D, hydrogen 1 in the gate insulating layer 130is diffused into the InGaZnO film as indicated by arrows 2 afterannealed. The hydrogen concentration at a pattern end 141 in the InGaZnOfilm is higher than the hydrogen concentration at a center 142 in theInGaZn film.

Desirably, annealing is performed before patterning the InGaZnO film, inorder to solve the aforementioned problem.

An amorphous oxide material having In as a main component is used forthe semiconductor layer 140, so that a TFT of excellent characteristicscan be obtained even manufactured at low temperature. The TFT 11according to this embodiment can also be manufactured at low temperaturefor increasing the area.

The state was observed in which the end portion of the InGaZnO film iscovered with the second channel protective film.

FIG. 16 is a diagram illustrating a cross section of a part of a TFTusing an SEM (Scanning Electron Microscope).

FIG. 17 is a diagram illustrating a cross section of a part of a TFTobserved with an SEM after the TFT is processed using dilute hydrogenfluoride.

These SEM images were obtained with JSM-6000F made by JEOL Ltd. Themicroscope is not limited particularly as long as the microscope is afield-emission SEM. It is difficult to observe the interface between thefirst channel protective film 151 and the second channel protective film152 by simply cutting the TFT (see FIG. 16). However, as illustrated inFIG. 17, dilute hydrogen fluoride (0.5%), for example, is applied to thecross section for 60 seconds, so that the interface between the firstchannel protective film 151 and the second channel protective film 152can be observed.

It is shown that the first channel protective film 151 in the upper partis in etch-back at etching the InGaZnO film by RIE mainly using achlorine gas, so that the end portion of the InGaZnO film is formed in avery gentle tapered shape.

HD-2300 made by Hitachi High-Technologies Corporation or the like isused to observe a TFT using a STEM (Scanning Transmission ElectronMicroscope) with no use of dilute hydrogen fluoride processing or thelike, so that the interface between the first channel protective film151 and the second channel protective film 152 can be observed.

Second Embodiment

FIG. 8 is a schematic view illustrating the configuration of a top gateTFT according to a second embodiment. FIG. 9 is a cross sectional viewon line IX-IX shown in FIG. 8.

As shown in FIG. 8 and FIG. 9, a TFT 311 includes a substrate 300, aninsulating layer 310 provided on the substrate 300, a semiconductorlayer 340 provided on the insulating layer 310 and containing oxide, anda gate insulating layer 350 provided on the semiconductor layer 340.

As illustrated FIG. 10D, described later, the TFT 311 further includes agate electrode 320 provided on the gate insulating layer 350, aninterlayer insulating film 370, a source electrode 361, and a drainelectrode 362. The interlayer insulating film 370 covers the gateelectrode 320 and a region except a source electrode contact region 340Sand a drain electrode contact region 340D in the semiconductor layer340. The source electrode 361 is provided on the source electrodecontact region 340S in the semiconductor layer 340. The drain electrode362 is provided on the drain electrode contact region 340D in thesemiconductor layer 340.

As illustrated in FIG. 8 and FIG. 9, the gate insulating layer 350includes a first gate insulating layer 351 (a first insulating film) anda second gate insulating layer 352 (a second insulating film). The firstgate insulating layer 351 (the first insulating film) covers thesemiconductor layer 140 except the source electrode contact region 340Sand the drain electrode contact region 340D. The second gate insulatinglayer 352 (the second insulating film) covers the first gate insulatinglayer 351 and edges 340E (the side surfaces) of the semiconductor layer340. The same material as the material of the first channel protectivefilm 151 in the first embodiment can be used for the material of thefirst gate insulating layer 351. The same material as the material ofthe second channel protective film 152 in the first embodiment can beused for the material of the second gate insulating layer 352. Theoxidation state of the second gate insulating layer 352 is higher thanthe oxidation state of the first gate insulating layer 351. As describedabove, the gate electrode 320 can be provided on at least one of thefirst insulating film (the first gate insulating layer 351) and thesecond insulating film (the second gate insulating layer 352).

Namely, the thin film transistor 311 includes the substrate 300, thesemiconductor layer 340, the first insulating film, the secondinsulating film, the gate electrode 320, the first electrode (the sourceelectrode 361), and the second electrode (the drain electrode 362). Thesemiconductor layer 340 is provided on the substrate 300. Thesemiconductor layer 340 contains an oxide including indium. Thesemiconductor layer 340 has a first portion 41, a second portion 42, anda middle portion 43. The semiconductor layer 340 has a top face 340U, afirst side face 340E1 of the middle portion 43, and a second side face340E2 of the middle portion 43. The top face 340U includes a firstregion (a source electrode contact region 340S) on the first portion 41,a second region (a drain electrode contact region 340D) on the secondportion 42, and an other region 3401 except the first region and thesecond region. The second side face 340E2 and the first side face 340E1are arranged side by side along a second direction vertical to a firstdirection from the first portion 41 toward the second portion 42, thefirst direction being in parallel with the major surface of thesubstrate 300.

The first insulating film covers the other region 3401. The secondinsulating film covers at least the first side face 340E and the secondside face 340E2. The second insulating film is formed under theconditions different from the conditions for the first insulating film.The gate electrode 320 faces the semiconductor layer 340. The firstelectrode is provided on the first region. The second electrode isprovided on the second region.

Although the substrate 300 and the insulating layer 310 are omitted inFIG. 8, the substrate 300 and the insulating layer 310 are provided onthe back side on the paper. The first gate insulating layer 351 isprovided on the back of the gate electrode 320 on the paper. The regionon which the second gate insulating layer 352 is provided is overlappedwith the region on which the gate electrode 320 is provided.

In the following, an exemplary manufacturing method for the TFT 311according to this embodiment will be described.

FIG. 10A to FIG. 10D are schematic cross sectional views illustratingthe process steps of a manufacturing method for the TFT 311 according tothe second embodiment. The cross sections in these drawings correspondto the cross section on line IX-IX in FIG. 8.

First, for example, SiO₂ is formed in a film for the insulating layer310 on the major surface of the substrate 300 made of PEN (polyethylenenaphtahalate) by sputtering, for example. After that, an InGaZnO film tobe the semiconductor layer 340 is formed in a thickness of 30 nm bysputtering. The first gate insulating layer 351 is continuously formedin a thickness of 30 nm by reactive sputtering using SiO₂ for a target.

As shown in FIG. 10A, the first gate insulating layer 351 and thesemiconductor layer 340 are processed in a predetermined shape.

After that, a SiO₂ film to be the second gate insulating layer 352 isformed in a thickness of 100 nm on the edges 340E of the semiconductorlayer 340 and the first gate insulating layer 351 by PE-CVD using a SiH₄gas and a N₂O gas (source gases). After that, a MoW alloy is formed in afilm in a thickness of 100 nm for the gate electrode 320.

As shown in FIG. 10B, the gate electrode 320, the second gate insulatinglayer 352, and the first gate insulating layer 351 are formed in apredetermined shape, and the source electrode contact region 340S andthe drain electrode contact region 340D of the semiconductor layer 340are exposed.

SiO₂ to be the interlayer insulating film 370 is then formed by PE-CVDusing a SiH₄ gas and a N₂O gas (source gases). In this film formation,SiO₂ is formed in a film under the film forming conditions with a highSiH₄ ratio in such a way that the resistance of the semiconductor layer340 contacted with the interlayer insulating film 370 is decreased.Alternatively, the resistance of the semiconductor layer 340 can bedecreased also using TEOS and an O₂ gas, instead of SiH₄ and N₂O.

As shown in FIG. 10C, openings connecting to the source electrodecontact region 340S and the drain electrode contact region 340D of thesemiconductor layer 340 are formed in the interlayer insulating film370. After that, a Mo film (50 nm), an Al film (200 nm), and a Mo film(50 nm) to be the source electrode 361 and the drain electrode 362 arestacked in the openings in this order.

As shown in FIG. 10D, these films are processed in a predeterminedshape, and then the TFT 311 is completed.

Also in the TFT 311 according to this embodiment, it is possible thatthe second insulating film (the second gate insulating layer 352)covering the edges 340E of the semiconductor layer 340 is formed to havean oxidation state higher than the oxidation state of the firstinsulating film (the first gate insulating layer 351) covering the topface of the semiconductor layer 340. Thus, it is possible to obtain thesimilar effect as that of the first embodiment.

Third Embodiment

FIG. 11 is a schematic view illustrating the configuration of a bottomgate TFT according to a third embodiment. FIG. 12 is a cross sectionalview on line XII-XII shown in FIG. 11.

This embodiment is another embodiment of the TFT according to the firstembodiment.

In a TFT 411 according to this embodiment, the width between two edges140E of a semiconductor layer 140 (the width along a second directionvertical to a first direction from a source electrode contact region140S toward a drain electrode contact region 140D, the first directionbeing in parallel with the major surface of an insulating layer 110, forexample) is wider than the width of a first channel protective film 451in the same direction (the width along the second direction). The otherconfigurations are the same as the configurations of the TFT accordingto the first embodiment. A channel protective film 450 includes thefirst channel protective film 451 and a second channel protective film452. The first channel protective film 451 covers the top face of thesemiconductor layer 140 except a source region (a source electrodecontact region 140S) in which the semiconductor layer 140 is contactedwith a source electrode 161 and a drain region (a drain electrodecontact region 140D) in which the semiconductor layer 140 is contactedwith a drain electrode 162. The second channel protective film 452covers the first channel protective film 451 and the edges 140E of thesemiconductor layer 140.

This TFT 411 can be manufactured as below. The semiconductor layer 140and the first channel protective film 451 are formed on the gateinsulating layer 130, SiO₂ that is the first channel protective film 451is then etched into a predetermined shape by RIE mainly using CF₄. Afterthat, an InGaZnO film to be the semiconductor layer 140 is processed ina shape larger than the shape of the first channel protective film 151.In this case, for the etchant for the InGaZnO film, dilute hydrochloricacid, oxalic acid, or the like can be used.

In the case where the width between the edges 140 of the semiconductorlayer 140 is made equal to the width of the first channel protectivefilm 451 and continuously processed in a predetermined shape, side etchis sometimes produced in the semiconductor layer 140 with respect to thefirst channel protective film 451. Although chlorine gas can also beused for processing the InGaZnO film, chlorine gas is highly poisonousand difficult to treat.

However, it is possible to readily manufacture the TFT 411 according tothis embodiment because side etch does not tend to be produced and nochlorine gas is used.

Also in the TFT 411 according to this embodiment, it is possible thatthe second insulating film (the second channel protective film 452)covering the edges 140E of the semiconductor layer 140 is formed to havean oxidation state higher than the oxidation state of the firstinsulating film (the first channel protective film 451) covering the topface of the semiconductor layer 140. Thus, it is possible to obtain thesimilar effect as that of the first embodiment.

Fourth Embodiment

FIG. 13 is a schematic view illustrating the configuration of a bottomgate TFT according to a fourth embodiment. FIG. 14 is a cross sectionalview on line XIV-XIV shown in FIG. 14.

This embodiment is another embodiment of the TFT according to the firstembodiment.

In a TFT 511 according to this embodiment, the width between edges 140Eof a semiconductor layer 140 (the width along a second direction) isshorter than the width of a first channel protective film 551 in thesame direction (the width along the second direction). The otherconfigurations are the same as the configurations of the TFT accordingto the first embodiment. A channel protective film 550 includes thefirst channel protective film 551 and a second channel protective film552. The first channel protective film 551 covers the top face of thesemiconductor layer 140 except a source region (a source electrodecontact region 140S) in which the semiconductor layer 140 is contactedwith a source electrode 161 and a drain region (a drain electrodecontact region 140D) in which the semiconductor layer 140 is contactedwith a drain electrode 162. The second channel protective film 552covers a first channel protective film 451 and the edges 140E of thesemiconductor layer 140.

This TFT 511 can also obtain the similar effect as that of the firstembodiment.

For the second channel protective film 552, a coating insulating layercan be used. A coating insulating layer is used, so that the InGaZnOfilm can be processed with no use of RIE or the like using a chlorinegas, which is an expensive process.

A coating film is used for the second channel protective film 552, sothat the coating film flows into the edges 140E to cover the edges 140Eeven though a side etch of about 1 μm is produced at the edges 140E ofthe semiconductor layer 140.

For the material of the second channel protective film 552, it wasrevealed that such a resin is suitable that the resin contains C(carbon), H (hydrogen), O (oxygen), N (nitrogen), and the like as maincomponents and further contains F (fluorine). It is considered that aresin, in which a part of the terminal end part of the molecule issubstituted from hydrogen to fluorine, is used, so that the resistanceof the InGaZnO film contacted with the second channel protective film552 is changed. It was revealed from experiments that the sheetresistance of the InGaZnO film is higher in about one digit in the casewhere the InGaZnO film is provided on a resin containing F than in thecase where the InGaZnO film is provided on a typical acrylic resin, inthe annealing range up to a temperature of 200° C. It is noted that thiseffect was obtained at 5 wt % or more of a fluorine load to a resin.

Fifth Embodiment

The TFTs according to the aforementioned embodiments have highly uniformcharacteristics and high reliability. An active matrix LCD (a displaydevice) can be formed using these TFTs.

FIG. 15A shows the equivalent circuit of a pixel circuit. FIG. 15B showsthe cross sectional structure of an active matrix LCD (display device600 a). Here, the case will be described where the TFT 11 according tothe first embodiment is used. The TFTs according to the otherembodiments can also be used.

The display device 600 a has a plurality of signal lines 601, and aplurality of gate lines 602 extending in a direction vertical to adirection in which the plurality of signal lines 601 extend. A singlepixel circuit is surrounded by a single signal line 601 and a singlegate line 602. The pixel circuit has a capacitor CS and a liquid crystallayer LC (display layer), for example, in addition to the TFT 11.

The active matrix LCD includes a liquid crystal cell 600 and a backlight640. The liquid crystal cell 600 includes an array substrate 610, acounter substrate 620, and a liquid crystal layer 630 (liquid crystallayer LC), for example. The array substrate 610 includes the TFT 11, apassivation film 611, and a pixel electrode 612, which are provided onone major surface of the array substrate 610. The counter substrate 620includes color filter layers 621 and 622 and a counter electrode 623,which are provided on one major surface of the counter substrate 620.The liquid crystal layer 630 is provided between the array substrate 610and the counter substrate 620. An alignment film 613 is provided on thepixel electrode 612 of the array substrate 610. An alignment film 624 isprovided on the counter electrode 623 of the counter substrate 620. Apolarizer 614 and a polarizer 625 are further provided, and the arraysubstrate 610 and the counter substrate 620 are provided therebetween.

Although the TFT using an InGaZnO film has a significantly highreliability, it is known that the application of an ultraviolet rayhaving energy greater than the band gap energy worsens thecharacteristics. The wavelength to worsen the characteristics is awavelength of 400 nm or less, and there are few worries aboutdeterioration in the case of using a typical backlight such as an LED,which does not emit rays having a wavelength of 400 nm or more.

However, it is known that a negative voltage is applied to the gateelectrode while applying rays to the TFT, causing a phenomenon that theTFT is worsened. This phenomenon also arises due to the application ofrays having a wavelength of about 400 nm, and it is difficult to takefull measures under the present techniques. Therefore, it is importantthat rays from the backlight are not allowed to enter the channel regionof the TFT.

The refractive index of the InGaZnO film is about 1.8 to 2, and therefractive index is larger than the refractive index, 1.4 to 1.5, ofSiO₂ or the like that is a surrounding transparent film. Thus, it isconsidered that when rays enter the InGaZnO film, the rays propagate theinside of the InGaZnO film according to the waveguide mode.Consequently, the pattern of the InGaZnO film is included in the gateelectrode when seen in plane so as to shield the InGaZnO film with thegate electrode against the rays, so that it is possible to improvereliability.

In the case where the TFT is formed on a resin such as PEN (polyethylenenaphtahalate), the gate electrode in the lower layer has the barriereffect against moisture in the resin layer or against hydrogen from thebarrier film from water under the gate electrode. Therefore, the InGaZnOlayer sensitive to moisture or hydrogen is provided in such a way thatthe InGaZnO layer is substantially included in the inside of the gateelectrode when seen in plane, so that it is possible that the InGaZnOlayer is made insensitive to moisture or hydrogen from the layer belowthe gate electrode.

Accordingly, the pattern of the InGaZnO film is included in the insideof the gate electrode when seen in plane, so that it is possible tofurther improve reliability.

The display device 600 a according to this embodiment includes the thinfilm transistor according to any one of the aforementioned embodimentsand a display layer (for example, the liquid crystal layer 630). Atleast one of optical emission and a change in the optical propertiesincluding at least one of birefringence, optical activity, scatteringproperty, diffraction property, and optical absorption occurs in thedisplay layer, according to at least one of a voltage and a currentsupplied through this thin film transistor.

In the description above, although the LCD is explained for an exampleof the display device, it is also possible to apply the TFTs accordingto the embodiments to other display devices such as an organicelectroluminescent display device, for example.

Sixth Embodiment

An exemplary manufacturing method for a TFT according to a sixthembodiment will be described.

FIG. 19 is a schematic plane view illustrating the configuration of abottom gate TFT (TFT 711) according to the sixth embodiment.

FIG. 20A to FIG. 20D are cross sectional views illustrating amanufacturing method for the TFT 711 according to the sixth embodiment.

FIG. 20A to FIG. 20D correspond to the cross section on line A-A′ shownin FIG. 19.

First, SiN and SiO₂ are formed in a film for an insulating layer 110 onthe major surface of a PEN substrate 100, for example, by PE-CVD, forexample. After that, an Al film and a Mo film to be a gate electrode 120are formed in a thickness of 150 nm and a thickness of 30 nm,respectively, by sputtering for stacking.

Subsequently, as illustrated in FIG. 20A, the gate electrode 120 isprocessed in a predetermined pattern. Photolithography is used for thisprocessing, and a mixed acid of phosphoric acid, acetic acid, and nitricacid is used for etching.

After that, a SiO₂ film to be a gate insulating layer 130 is formed in athickness of 200 nm, for example, by plasma CVD using SiH₄ and N₂O, forexample. The film forming temperature in this film formation is atemperature of 160° C. in consideration of the heat-resisting propertiesof PEN of the substrate 100.

On this SiO₂ film, an InGaZnO film (an IN₂O₃—Ga₂O₃—ZnO film, forexample) to be a semiconductor layer 140 is formed in a thickness of 30nm, for example, by reactive DC sputtering. In this film formation, thecomposition ratio of targets used is 1:1:1 at the atom number ratio ofIn:Ga:Zn. This film is formed in an atmosphere containing oxygen andargon, and the ratio of oxygen is about 1%, for example, to argon. Thefilm forming temperature is a temperature of about a few tens° C.,because heat treatment or the like is not particularly applied.

A SiO₂ film to be a first channel protective film 151 is formed in athickness of 30 nm, for example, by PE-CVD using a SiH₄ gas and a N₂Ogas (source gases). Desirably, the semiconductor layer 140 and the firstchannel protective film 151 are formed in Vacuum In-situ Processingwithout exposing the interface to atmosphere, as much as possible. Thefirst channel protective film 151 is used for a barrier film againstwater in processing the semiconductor layer 140 described later.

Subsequently, as shown in FIG. 20B, the first channel protective film151 and the semiconductor layer 140 are continuously processed in apredetermined shape. For example, the first channel protective film 151and the semiconductor layer 140 are processed by RIE mainly using achlorine gas. In consideration of the coverage of the second channelprotective film 152 in the process steps described later, no side etchis to be produced in the semiconductor layer 140 (the InGaZnO film).

After this processing, a SiO₂ film is formed for a second channelprotective film 152 throughout the surface by PE-CVD using a SiH₄ gasand a N₂O gas (source gases). For the film forming conditions in thisfilm formation, such conditions are used that the gas ratio of SiH₄/N₂Ois decreased with respect to the aforementioned film forming conditionsfor the first channel protective film 151. Namely, the second channelprotective film 152 is formed under the conditions that the resistanceof the InGaZnO film is increased. The conditions are important.

After that, as shown in FIG. 20C, the second channel protective film 152and the first channel protective film 151 are processed in apredetermined shape in such a way that the contact region of thesemiconductor layer 140 is exposed. This processing is performed by RIEusing a CF₄ gas or a CHF₃ gas or CF₄ and CHF₃ mixed gas for a maincomponent. Since the InGaZnO film is hardly processed in typical RIEusing a CF₄ gas or a CHF₃ gas or CF₄ and CHF₃ mixed gas, the contacthole to gate electrode 120 can be formed (etching the second channelprotective film 152 and the first channel protective film 151 and gateinsulating layer 130) at etching the second channel protective film 152and the first channel protective film 151 simultaneously.

After this processing, a Mo film (a thickness of 30 nm), an Al film (athickness of 200 nm), and a Mo film (a thickness of 50 nm) to be asource electrode 161 and a drain electrode 162 are formed by sputtering.

As illustrated in FIG. 20D, these films are formed in a predeterminedshape, and then the TFT 711 is completed. Since the TFT 711 immediatelyafter processed is damaged by ultraviolet rays or the like inprocessing, annealing (heat treatment) is performed in an annealingchamber at a temperature of about 150° C. for one hour.

A manufacturing method for a thin film transistor according to anembodiment includes: forming a first insulating film under first formingconditions; and forming a second insulating film under conditionsdifferent from the first forming conditions.

According to the embodiment, it is possible to provide a highly reliablethin film transistor using an oxide semiconductor, a manufacturingmethod for the same, and a display device.

In the specification of the application, “perpendicular” and “parallel”refer to not only strictly perpendicular and strictly parallel but alsoinclude, for example, the fluctuation due to manufacturing processes,etc. It is sufficient to be substantially perpendicular andsubstantially parallel.

Hereinabove, exemplary embodiments of the invention are described withreference to specific examples. However, the invention is not limited tothese specific examples. For example, the specific configurations ofcomponents constituting a thin film transistor, a manufacturing methodfor the same, a display device, and a manufacturing method for the samecan be included in the scope of the invention, as long as a personskilled in the art may appropriately select configurations from thepublicly known ranges to similarly implement the invention and to obtainthe similar effect.

Further, any two or more components of the specific examples may becombined within the extent of technical feasibility and are included inthe scope of the embodiments to the extent that the spirit of theembodiments is included.

Moreover, all thin film transistors, manufacturing methods for the same,and display devices, which can be implemented by a person skilled in theart to appropriately change the design based on the thin filmtransistors, the manufacturing methods for the same, and the displaydevice described above, which are described for the embodiments of theinvention, are within the scope of the invention to the extent that thepurport of the invention is included.

Furthermore, various modifications and alterations within the spirit ofthe invention will be readily apparent to those skilled in the art.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

1. A thin film transistor comprising: a substrate; a semiconductor layerprovided on the substrate, the semiconductor layer being made of anoxide having indium for a main component, the semiconductor layer havinga top face facing the substrate and a pair of side face, the top facehaving a first region, a second region, and an other region except thefirst region and the second region; a first insulating film covering theother region of the semiconductor layer; a second insulating filmcovering at least the pair of side surfaces of the semiconductor layer,the second insulating film being formed under a condition different froma condition for the first insulating film; a gate electrode provided onthe first insulating film and the second insulating film or providedbelow the semiconductor layer; a source electrode provided on the firstregion; and a drain electrode provided on the second region, the drainelectrode facing the source electrode, the drain electrode and thesource electrode sandwiching the pair of the side surfaces of thesemiconductor layer.
 2. The transistor according to claim 1, wherein thesecond insulating film is formed using conditions including at least oneof: a flow ratio smaller than a flow ratio of a source gas in formingthe first insulating film; a film forming rate smaller than a filmforming rate in forming the first insulating film; and a film formingtemperature lower than a film forming temperature in forming the firstinsulating film.
 3. The transistor according to claim 1, wherein thesecond insulating film includes silicon oxide.
 4. The transistoraccording to claim 1, further comprising a gate insulating layer, thegate electrode being provided between the substrate and thesemiconductor layer, and the gate insulating layer being providedbetween the gate electrode and the semiconductor layer.
 5. Thetransistor according to claim 4, wherein a distance between the pair ofthe side surfaces is shorter than a width of the gate electrode along afirst direction from one of the pair of the side surfaces toward theother of the pair of the side surfaces.
 6. The transistor according toclaim 5, wherein a distance between the pair of the side surfaces islonger than a width along the direction of the first insulating film. 7.The transistor according to claim 1, wherein the gate electrode isprovided on at least one of the first insulating film and the secondinsulating film.
 8. The transistor according to claim 1, wherein thesecond insulating film further covers at least a part of the firstinsulating film.
 9. The transistor according to claim 1, wherein thesecond insulating film includes a resin containing fluorine at aconcentration of 5 wt % or more.
 10. The transistor according to claim1, wherein the semiconductor layer further contains at least one ofgallium (Ga), zinc (Zn), tin (Sn), and silicon (Si).
 11. The transistoraccording to claim 1, wherein a thickness of the first insulating filmis 10 nanometer or more.
 12. The transistor according to claim 1,wherein a thickness of the first insulating film is 50 nanometers orless.
 13. The transistor according to claim 1, wherein an oxygenconcentration of the second insulating film is higher than an oxygenconcentration of the first insulating film.
 14. The transistor accordingto claim 1, wherein the first insulating film is formed with a gascontaining silicon and oxygen with a first value of a ratio of a siliconquantity to an oxygen quantity; and the second insulating film is formedwith a gas containing silicon and oxygen with a second value of a ratioof a silicon quantity to an oxygen quantity, the second value beinglower than the first value.
 15. The transistor according to claim 1,wherein the first insulating film is formed using a SiH₄ gas and a N₂Ogas with a first value of a ratio of a SiH₄ gas flow rate to a N₂O gasflow rate; and the second insulating film is formed using a SiH₄ gas anda N₂O gas with a second value of a ratio of a SiH₄ gas flow rate to aN₂O gas flow rate, the second value being lower than the first value.16. A manufacturing method for a thin film transistor, comprising:processing including: forming a semiconductor layer made of an oxidehaving indium for a main component on a gate electrode on a substratevia a gate insulating layer, forming a first insulating film on a topface except a source electrode contact region and a drain electrodecontact region of the semiconductor layer, and forming a secondinsulating film covering at least a pair of side surfaces of thesemiconductor layer under a condition different from a condition for thefirst insulating film; or forming a semiconductor layer made of an oxidehaving indium for a main component on a substrate, forming a firstinsulating film on a top face except a source electrode contact regionand a drain electrode contact region of the semiconductor layer, forminga second insulating film covering at least a pair of side surfaces ofthe semiconductor layer under a condition different from a condition forthe first insulating film, and forming a gate electrode on the secondinsulating film; forming a source electrode on the source electrodecontact region of the semiconductor layer; and forming a drain electrodeon the drain electrode contact region of the semiconductor layer so asto face the source electrode to sandwich a part of the side surfaces ofthe semiconductor layer.
 17. The method according to claim 16, whereinthe forming the second insulating film includes using conditionsincluding at least one of: a flow rate of a gas containing Si, the flowrate being smaller than a flow rate of a source gas containing Si in theforming the first insulating film; a film forming rate smaller than afilm forming rate in the forming the first insulating film; and a filmforming temperature lower than a film forming temperature in the formingthe first insulating film.
 18. The method according to claim 16,wherein, annealing at a highest temperature in forming process of thethin film transistor for 10 minutes or more is performed after theforming the second insulating film; or annealing at the highesttemperature in forming process of the thin film transistor for 10minutes or more is performed in the forming the second insulating film.19. The method according to claim 16, wherein the semiconductor layer isformed by processing performed after being formed on the substrate andannealed.
 20. A display device comprising: a thin film transistorincluding: a substrate; a semiconductor layer provided on the substrate,the semiconductor layer being made of an oxide having indium for a maincomponent, the semiconductor layer having a top face facing thesubstrate and a pair of side face, the top face having a first region, asecond region, and an other region except the first region and thesecond region; a first insulating film covering the other region of thesemiconductor layer; a second insulating film covering at least the pairof side surfaces of the semiconductor layer, the second insulating filmbeing formed under a condition different from a condition for the firstinsulating film; a gate electrode provided on the first insulating filmand the second insulating film or below the semiconductor layer; asource electrode provided on the first region; and a drain electrodeprovided on the second region, the drain electrode facing the sourceelectrode, the drain electrode and the source electrode sandwiching thepair of the side surfaces of the semiconductor layer; and a displaylayer configured to cause at least one of optical emission and a changein an optical property including at least one of birefringence, opticalactivity, scattering property, diffraction property, and opticalabsorption, according to at least one of a voltage and a currentsupplied through the thin film transistor.